ASIC Design Engineer
Ottawaonsitemid
via Greenhouse
About this role
About the Role
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting-edge technologies.
Locations: Ottawa, Ontario, Canada and Córdoba, Cordoba, Argentina
What you Will Do:
Design and implement digital circuits using HDL (Verilog/ System Verilog).
Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis
Optimize designs for performance, power, and area (PPA) requirements.
Perform RTL simulation and verification to ensure design functionality.
Participate in design reviews and provide technical guidance to team members.…
Read the full description on Celerocommunicationsinc's site →
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, teams
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in Ottawa. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
pythonteams
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